diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 02:41:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-08 15:52:21 +0000 |
| commit | 94246660f19059eee418e0b8257c7b13888757d1 (patch) | |
| tree | da1f556c81f1755d2ab6badd03f551c397eb0351 /src/soc/amd | |
| parent | 9a070dc7468cce530a70eb58e7a12426a9aa741e (diff) | |
soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope
The PCI root complex itself isn't on an enumerable bus, so without
providing an _STA method, the device will still be assumed to be present
and visible, so this won't change behavior. This also brings Picasso
more in line with Cezanne and newer SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/acpi/northbridge.asl | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 5cbe950235..bec9b46d8e 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -2,11 +2,6 @@ /* Describe the Northbridge devices */ -Method(_STA, 0, NotSerialized) -{ - Return(0x0f) /* Status is visible */ -} - /* PCI Routing Table */ Name(PR0, Package(){ /* Bus 0, Dev 0x00 - F2: IOMMU */ |