src/soc to src/superio: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 12 insertions, 12 deletions

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index 80ce9466ec..ac79cc9e11 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -127,7 +127,7 @@ static void fch_init_resets(void)
 	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
 }
 
-/* configure the genral purpose PCIe clock outputs according to the devicetree settings */
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
 	const struct soc_amd_cezanne_config *cfg = config_of_soc();
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index e948bca903..292cdd8318 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -29,7 +29,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 63898308e7..4fcd3f71a3 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -22,7 +22,7 @@ struct __packed usb2_phy_tune {
 	uint8_t	sq_rx_tune;
 	/* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
 	uint8_t	tx_fsls_tune;
-	/* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */
+	/* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */
 	uint8_t	tx_pre_emp_amp_tune;
 	/* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
 	uint8_t	tx_pre_emp_pulse_tune;
@@ -99,7 +99,7 @@ struct soc_amd_picasso_config {
 	 * If sb_reset_i2c_peripherals() is called, this devicetree register
 	 * defines which I2C SCL will be toggled 9 times at 100 KHz.
 	 * For example, should we need I2C0 and  I2C3 have their peripheral
-	 * devices reseted by toggling SCL, use:
+	 * devices reset by toggling SCL, use:
 	 *
 	 * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
 	 */
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index 711091c5c5..44acc817ef 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -175,7 +175,7 @@ static void al2ahb_clock_gate(void)
 	write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
 }
 
-/* configure the genral purpose PCIe clock outputs according to the devicetree settings */
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
 	const struct soc_amd_picasso_config *cfg = config_of_soc();
diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h
index 28062b689e..2ea35a940b 100644
--- a/src/soc/amd/picasso/include/soc/platform_descriptors.h
+++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h
@@ -7,7 +7,7 @@
 #include <platform_descriptors.h>
 #include <FspsUpd.h>
 
-/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG.
+/* These temporary macros apply to emmc0_mode field in FSP_S_CONFIG.
  * TODO: Remove when official definitions arrive. */
 #define SD_DISABLE		0
 #define SD_LOW_SPEED		1
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 78ce889e5d..f7ea782da9 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -56,7 +56,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 82c54371c5..b870baeb88 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -46,7 +46,7 @@ struct soc_amd_stoneyridge_config {
 	 * If sb_reset_i2c_peripherals() is called, this devicetree register
 	 * defines which I2C SCL will be toggled 9 times at 100 KHz.
 	 * For example, should we need I2C0 and  I2C3 have their peripheral
-	 * devices reseted by toggling SCL, use:
+	 * devices reset by toggling SCL, use:
 	 *
 	 * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
 	 */
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index d80aeb2a09..d5231ad5d5 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -400,19 +400,19 @@ void domain_read_resources(struct device *dev)
 	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 
 	/*
-	 * 0x100000 (1MiB) -> low top useable RAM
+	 * 0x100000 (1MiB) -> low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
 	ram_resource(dev, idx++, (1 * MiB) / KiB,
 			(mem_useable - (1 * MiB)) / KiB);
 
-	/* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */
+	/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
 	reserved_ram_resource(dev, idx++, mem_useable / KiB,
 					(tom.lo - mem_useable) / KiB);
 
 	/* If there is memory above 4GiB */
 	if (high_tom.hi) {
-		/* 4GiB -> high top useable */
+		/* 4GiB -> high top usable */
 		if (uma_base >= (4ull * GiB))
 			high_mem_useable = uma_base;
 		else
@@ -422,7 +422,7 @@ void domain_read_resources(struct device *dev)
 		ram_resource(dev, idx++, (4ull * GiB) / KiB,
 				((high_mem_useable - (4ull * GiB)) / KiB));
 
-		/* High top useable RAM -> high top RAM */
+		/* High top usable RAM -> high top RAM */
 		if (uma_base >= (4ull * GiB)) {
 			reserved_ram_resource(dev, idx++, uma_base / KiB,
 						uma_size / KiB);