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author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-29 14:01:01 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-28 13:33:30 +0000 |
commit | 595202c304d14e17b1ea1514169346d7cc637206 (patch) | |
tree | dd5d67885d1b40669c11a733178bb3d5f8605052 /src/soc/amd/stoneyridge | |
parent | 3b0667dd2a386fd13765cb047ef7484ba169a10d (diff) |
soc/intel/denverton_ns: Add ACPI T-States and P-States
Also make soc_get_tss_table public and weak instead of static
in intelblock so it can be overridden in denverton.
Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
0 files changed, 0 insertions, 0 deletions