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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-26 16:19:36 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 14:49:16 +0000 |
| commit | b77c76c271f19115230411bf8f54defd7f154b73 (patch) | |
| tree | 22a91e6bf42f95142aacb4a40cd4884d84531f8a /src/soc/amd/stoneyridge/southbridge.c | |
| parent | 1d9a46ba9a289691325d2dece09c3d4ebd15439a (diff) | |
amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define
various PCI config space registers. These are duplicated from AMD's
FchCarrizo.asl file.
BUG=b:77602074
Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28768
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
0 files changed, 0 insertions, 0 deletions