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authorRaul E Rangel <rrangel@chromium.org>2021-06-25 11:07:23 -0600
committerMartin Roth <martinroth@google.com>2021-07-18 00:24:09 +0000
commitd373d5d92f872e59248d4bd7225ae80616100f35 (patch)
tree3bff51f14ea25e14b5648afbd0ca1f2cf85996d1 /src/soc/amd/stoneyridge/reset.c
parente6dd5dc4ea27d6c734ff01f2812a30591bcefd36 (diff)
soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
This change will make it so the standard rdev readat call will use the SPI DMA controller if the alignment is correct, and the transfer size is larger than 64 bytes. There is a magic bit that needs to be set for the SPI DMA controller to function correctly. This is only available in RN/CZN+. BUG=b:179699789 TEST=Boot guybrush to OS. This reduces loading verstage by 40ms, verifying RW by 500us and loading romstage by 500 us. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/reset.c')
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