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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-07 20:45:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 09:52:16 +0000 |
| commit | 59431176471beac2e074cf0ebca50c98c1ab50c8 (patch) | |
| tree | f350d86c863125d2d5ad862be42d68212c40ab08 /src/soc/amd/stoneyridge/psp.c | |
| parent | ba41ee1f0a74cf6b0ed0c068b6560e60f7d760eb (diff) | |
soc/intel/tigerlake: Configure RP setting
Add LTR and AER configuration to the root ports config.
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/psp.c')
0 files changed, 0 insertions, 0 deletions