soc/amd/stoneyridge: Add XHCI PM register access functions

Add functions to access the XHCI PM MMIO registers.

Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

2 files changed, 7 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 53eb7120ae..64a9b30f2f 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -31,6 +31,7 @@
 #define AMD_SB_ACPI_MMIO_ADDR		0xfed80000
 #define APU_SMI_BASE			0xfed80200
 #define PM_MMIO_BASE			0xfed80300
+#define XHCI_ACPI_PM_MMIO_BASE		0xfed81c00
 #define APU_UART0_BASE			0xfedc6000
 #define APU_UART1_BASE			0xfedc8000
 
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d9114728e3..f840fd9296 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -312,6 +312,12 @@ void smi_write16(uint8_t offset, uint16_t value);
 void smi_write32(uint8_t offset, uint32_t value);
 uint16_t pm_acpi_pm_cnt_blk(void);
 uint16_t pm_acpi_pm_evt_blk(void);
+void xhci_pm_write8(uint8_t reg, uint8_t value);
+uint8_t xhci_pm_read8(uint8_t reg);
+void xhci_pm_write16(uint8_t reg, uint16_t value);
+uint16_t xhci_pm_read16(uint8_t reg);
+void xhci_pm_write32(uint8_t reg, uint32_t value);
+uint32_t xhci_pm_read32(uint8_t reg);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 void bootblock_fch_early_init(void);