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author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-03 21:38:14 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 22:05:59 +0000 |
commit | 7e703d77b2cb2189863d2a2e87f7de2913e20307 (patch) | |
tree | 2667898e7a0ab41ad613bf26129e03b071513592 /src/soc/amd/stoneyridge/include | |
parent | 757d645cb069f1759303467efb9753fcdd847da4 (diff) |
soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
0 files changed, 0 insertions, 0 deletions