summaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge/chip.h
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-02-12 00:43:20 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-13 20:57:23 +0000
commit604ffa6d23463c17f83e26d1f52c48865487546f (patch)
tree51c66d452ad155a16be86a730e064a6083088399 /src/soc/amd/stoneyridge/chip.h
parent5f5b7ddbf3f80cbd4135aaa0d668387acf40d7a5 (diff)
soc/amd: introduce and use common IOAPIC IDs
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as IOAPIC IDs and Picasso had Kconfig options to configure that, but still used the common SMBus controller code that used CONFIG_MAX_CPUS as ID for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a mismatch between the ID that gets written into the FCH IOAPIC register and the ID in the corresponding ACPI table. In order to avoid that add defines to each SOC's southbridge.c and use them in all soc/amd code. Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
0 files changed, 0 insertions, 0 deletions