diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 15:23:25 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-28 08:59:11 +0000 |
| commit | ae7ac8a72372e4099bcf0667b5f97b4a223da48d (patch) | |
| tree | ae4d809a4cfa01711a76da4a5b5ca234f80ff778 /src/soc/amd/stoneyridge/acpi | |
| parent | fa5f9b5aff2279d6304a8b197e12714934025575 (diff) | |
ACPI: Separate ChromeOS NVS in ASL
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.
More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 252ceda911..7a48dd57f8 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -42,7 +42,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve) FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM EH10, 32, // 0x30 - EHCI BAR - /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> } |