diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-13 18:56:50 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 23:01:08 +0000 |
| commit | cbf290c692b254badb091506cc11855b52ddf266 (patch) | |
| tree | 4e2a1029a8613d97263f5ffe823e810abf90d3d3 /src/soc/amd/sabrina/include | |
| parent | 1c3b2a706e536c0ed11fd1d7073131fcf4a2029a (diff) | |
soc/amd/sabrina: drop CPPC code
The CPPC feature isn't available on the Sabrina SoC, so drop the
corresponding code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/include')
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/cppc.h | 15 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/msr.h | 17 |
2 files changed, 0 insertions, 32 deletions
diff --git a/src/soc/amd/sabrina/include/soc/cppc.h b/src/soc/amd/sabrina/include/soc/cppc.h deleted file mode 100644 index 7ae94bfb3d..0000000000 --- a/src/soc/amd/sabrina/include/soc/cppc.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -#ifndef AMD_SABRINA_CPPC_H -#define AMD_SABRINA_CPPC_H - -#include <types.h> -#include <acpi/acpigen.h> - -struct cppc_config; -void cpu_init_cppc_config(struct cppc_config *config, u32 version); -void generate_cppc_entries(unsigned int core_id); - -#endif /* AMD_SABRINA_CPPC_H */ diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h index 48c2fd13ec..bdc7a14c40 100644 --- a/src/soc/amd/sabrina/include/soc/msr.h +++ b/src/soc/amd/sabrina/include/soc/msr.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #ifndef AMD_SABRINA_MSR_H #define AMD_SABRINA_MSR_H @@ -23,21 +21,6 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 |