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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-12 23:18:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 22:18:17 +0000 |
| commit | b1fe9de74d420cf7193135c2b6d034bf06dabe94 (patch) | |
| tree | 414d6251c4e22441c9b7a9bf2967f7ba84131efa /src/soc/amd/sabrina/chipset.cb | |
| parent | a48f29192dd01e3be490394b265b90b619e81d4a (diff) | |
soc/amd/sabrina: add additional UART controllers
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of
the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/chipset.cb')
| -rw-r--r-- | src/soc/amd/sabrina/chipset.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset.cb index 486f42fb5c..8c6fab96c5 100644 --- a/src/soc/amd/sabrina/chipset.cb +++ b/src/soc/amd/sabrina/chipset.cb @@ -110,5 +110,8 @@ chip soc/amd/sabrina device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedca000 alias uart_1 off end + device mmio 0xfedce000 alias uart_2 off end + device mmio 0xfedcf000 alias uart_3 off end + device mmio 0xfedd1000 alias uart_4 off end device mmio 0xfedd5000 alias emmc off end end |