diff options
| author | Jon Murphy <jpmurphy@google.com> | 2022-02-24 14:37:04 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-28 13:29:24 +0000 |
| commit | 6e368f79ecc42a60eb37b77535d35136afc2e106 (patch) | |
| tree | d6ba0d9ef48069df287eed311c24f67b192da574 /src/soc/amd/sabrina/chipset.cb | |
| parent | 96bb0ba9e72297e98ecd2c2ce88cb4037d496ee5 (diff) | |
soc/amd/sabrina: Add XHCI configuration
Add xhci 2 controller support for additional USB port/ Dummy setting
BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/sabrina/chipset.cb')
| -rw-r--r-- | src/soc/amd/sabrina/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset.cb index c477a17d3d..bd5a60daab 100644 --- a/src/soc/amd/sabrina/chipset.cb +++ b/src/soc/amd/sabrina/chipset.cb @@ -64,7 +64,7 @@ chip soc/amd/sabrina end device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C - device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function + device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID end device pci 14.0 alias smbus on end # primary FCH function |