diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-08-03 00:10:03 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-08 19:40:59 +0000 |
| commit | 18a3c230ff4ab06dda46ebac9902d198721909d9 (patch) | |
| tree | b30973e53cc052fbf9ca7285862ca6e717852aa2 /src/soc/amd/picasso | |
| parent | 8677d2ddb82e79330e24e1355ab4fbe3360aad1a (diff) | |
soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
To have both the PCI function number and the register offset into the
config space of that function of the data fabric device in the data
fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN
and DF_REG_REG macros. The DF_REG_ID macro is used for register
definitions where both the function number and the register offset are
specified, and the DF_REG_FN and DF_REG_REG macros are used to extract
the function number and the register offset from the register defines.
This will allow having one define for accessing an indexed group of
registers that are on different functions of the data fabric device.
TEST=MMIO resources read from the data fabric's MMIO decode registers
don't change on Mandolin and the ACPI CRAT table is also identical.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63a284b26081c170a217b082b100c482f6158e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/agesa_acpi.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/data_fabric.h | 21 |
2 files changed, 14 insertions, 13 deletions
diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 7482a03991..ed0b4569a4 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -64,10 +64,10 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG; dram_map_idx++) { dram_base_reg = - data_fabric_read32(0, DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); + data_fabric_read32(DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); if (dram_base_reg & DRAM_BASE_REG_VALID) { - dram_limit_reg = data_fabric_read32(0, DF_DRAM_LIMIT(dram_map_idx), + dram_limit_reg = data_fabric_read32(DF_DRAM_LIMIT(dram_map_idx), IOMS0_FABRIC_ID); memory_length = ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 @@ -85,7 +85,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, } if (dram_base_reg & DRAM_BASE_HOLE_EN) { - dram_hole_ctl = data_fabric_read32(0, D18F0_DRAM_HOLE_CTL, + dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL, IOMS0_FABRIC_ID); hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); size_below_hole = hole_base - memory_base; diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 44463715d7..382de8a73e 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -3,20 +3,21 @@ #ifndef AMD_PICASSO_DATA_FABRIC_H #define AMD_PICASSO_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x5C -#define DF_FICAD_LO 0x98 -#define DF_FICAD_HI 0x9C +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) #define IOMS0_FABRIC_ID 9 @@ -47,15 +48,15 @@ union df_ficaa { }; -#define D18F0_VGAEN 0x80 +#define D18F0_VGAEN DF_REG_ID(0, 0x80) #define VGA_ADDR_ENABLE BIT(0) -#define D18F0_DRAM_HOLE_CTL 0x104 +#define D18F0_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) #define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) -#define D18F0_DRAM_BASE0 0x110 +#define D18F0_DRAM_BASE0 DF_REG_ID(0, 0x110) #define DRAM_BASE_REG_VALID BIT(0) #define DRAM_BASE_HOLE_EN BIT(1) #define DRAM_BASE_INTLV_CH_SHFT 4 @@ -65,7 +66,7 @@ union df_ficaa { #define DRAM_BASE_ADDR_SHFT 12 #define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT) -#define D18F0_DRAM_LIMIT0 0x114 +#define D18F0_DRAM_LIMIT0 DF_REG_ID(0, 0x114) #define DRAM_LIMIT_DST_ID_SHFT 0 #define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT) #define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 |