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authorFelix Held <felix-coreboot@felixheld.de>2020-07-23 18:22:30 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-07-26 17:08:00 +0000
commit3a7389ef1055769f7c6d9ce53025b69e69f15349 (patch)
tree5afa328c88f1b7a65dbe8ec2c83d179d5eb6ea17 /src/soc/amd/picasso
parent4e58ce15351d95aabc529b6affe91d2b0a7993d0 (diff)
amd/picasso: rework USB2 PHY tune parameter handling
BUG=b:161923068 Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/chip.h9
-rw-r--r--src/soc/amd/picasso/fsp_params.c13
2 files changed, 9 insertions, 13 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index d3c9a0721b..64258b24ca 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -37,6 +37,8 @@ struct __packed usb2_phy_tune {
uint8_t tx_res_tune;
};
+#define USB_PORT_COUNT 6
+
struct soc_amd_picasso_config {
struct soc_amd_common_config common_config;
/*
@@ -134,12 +136,7 @@ struct soc_amd_picasso_config {
uint8_t xhci0_force_gen1;
uint8_t has_usb2_phy_tune_params;
- struct usb2_phy_tune usb_2_port_0_tune_params;
- struct usb2_phy_tune usb_2_port_1_tune_params;
- struct usb2_phy_tune usb_2_port_2_tune_params;
- struct usb2_phy_tune usb_2_port_3_tune_params;
- struct usb2_phy_tune usb_2_port_4_tune_params;
- struct usb2_phy_tune usb_2_port_5_tune_params;
+ struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT];
};
typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index d280bffc47..8e6703e436 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -98,17 +98,16 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
const struct soc_amd_picasso_config *cfg)
{
- size_t num = sizeof(struct usb2_phy_tune);
+ ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT);
scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
if (cfg->has_usb2_phy_tune_params) {
- memcpy(scfg->fch_usb_2_port0_phy_tune, &cfg->usb_2_port_0_tune_params, num);
- memcpy(scfg->fch_usb_2_port1_phy_tune, &cfg->usb_2_port_1_tune_params, num);
- memcpy(scfg->fch_usb_2_port2_phy_tune, &cfg->usb_2_port_2_tune_params, num);
- memcpy(scfg->fch_usb_2_port3_phy_tune, &cfg->usb_2_port_3_tune_params, num);
- memcpy(scfg->fch_usb_2_port4_phy_tune, &cfg->usb_2_port_4_tune_params, num);
- memcpy(scfg->fch_usb_2_port5_phy_tune, &cfg->usb_2_port_5_tune_params, num);
+ for (size_t i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {
+ memcpy(scfg->fch_usb_2_port_phy_tune[i],
+ &cfg->usb_2_port_tune_params[i],
+ sizeof(scfg->fch_usb_2_port_phy_tune[0]));
+ }
}
}