diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-06-11 16:57:23 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-18 16:43:09 +0000 |
| commit | 34fb9399de46574b4a6d8a3a822f430061216137 (patch) | |
| tree | 9887ada2ad7dc98121383f035e6fae35925c4325 /src/soc/amd/picasso/acpi | |
| parent | ef3395d990bbf1118a8d4e367a986bdbc92b1820 (diff) | |
soc/amd/picasso: Add ability to enable/disable UART to device tree
If we are not using the UARTs or they don't have the correct GPIOs
configured we should let the mainboard disable them.
BUG=b:153001807
TEST=Dump SSDT and see UART device is disabled
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/acpi')
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_fch.asl | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 0bc9b8c0b0..0801c11722 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,11 +122,6 @@ Device (FUR0) Return (Local0) } } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (FUR1) { @@ -158,11 +153,6 @@ Device (FUR1) { Return (Local0) } } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (FUR2) { @@ -194,11 +184,6 @@ Device (FUR2) { Return (Local0) } } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (FUR3) { @@ -230,11 +215,6 @@ Device (FUR3) { Return (Local0) } } - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } } Device (I2C2) { |