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authorMartin Roth <martinroth@chromium.org>2020-10-28 11:52:30 -0600
committerFelix Held <felix-coreboot@felixheld.de>2020-11-06 18:53:05 +0000
commit5632c6bc020b02868e21714ea990d550e44e91d3 (patch)
tree3997e0102f6449c38cdd27a14ba04346b22e42fd /src/soc/amd/picasso/Kconfig
parent03d06d3bcd368a8e635e3279d4f17336f09adef8 (diff)
soc/amd/picasso: Set vboot hashing block size to 36k
On picasso's psp_verstage, the vboot hash is being calculated by hardware using relatively expensive system calls. By increasing the block size, we can save roughly 150ms of boot and S3 resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
-rw-r--r--src/soc/amd/picasso/Kconfig16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index bae2d2868a..5ae0a2a58f 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -535,6 +535,22 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD.
+config VBOOT_HASH_BLOCK_SIZE
+ hex
+ default 0x9000
+ depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
+ help
+ Because the bulk of the time in psp_verstage to hash the RO cbfs is
+ spent in the overhead of doing svc calls, increasing the hash block
+ size significantly cuts the verstage hashing time as seen below.
+
+ 4k takes 180ms
+ 16k takes 44ms
+ 32k takes 33.7ms
+ 36k takes 32.5ms
+ There's actually still room for an even bigger stack, but we've
+ reached a point of diminishing returns.
+
config CMOS_RECOVERY_BYTE
hex
default 0x51