diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-10 00:03:37 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-23 22:45:35 +0000 |
| commit | f0b6255446a44f902da88b0f137652753d831fa4 (patch) | |
| tree | d6c5f234caad71fcfae3e43458101528e5e061ee /src/soc/amd/phoenix | |
| parent | 586b1c8da06fe34f91c747440730b31428248b34 (diff) | |
soc/amd/phoenix: introduce and use pstate_msr bitfield struct
Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs and use this
bitfield struct in get_pstate_core_freq and get_pstate_core_power. The
signature of those two function will be changed in a follow-up commit.
PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference as
well as the reference code. This patch also adds and uses the cpu_vid_8
bit which is the 9th bit of the voltage ID specified in the SVI3 spec.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia024d32ae75cf2ffbc2a2e86a8b3af3dc6cbad61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/phoenix')
| -rw-r--r-- | src/soc/amd/phoenix/acpi.c | 20 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/include/soc/msr.h | 24 |
2 files changed, 25 insertions, 19 deletions
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 1e9af9eb26..ac21851cfa 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -102,13 +102,15 @@ uint32_t get_pstate_core_freq(msr_t pstate_def) { uint32_t core_freq, core_freq_mul, core_freq_div; bool valid_freq_divisor; + union pstate_msr pstate_reg; + + pstate_reg.raw = pstate_def.raw; /* Core frequency multiplier */ - core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK; + core_freq_mul = pstate_reg.cpu_fid_0_7; /* Core frequency divisor ID */ - core_freq_div = - (pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT; + core_freq_div = pstate_reg.cpu_dfs_id; if (core_freq_div == 0) { return 0; @@ -139,18 +141,18 @@ uint32_t get_pstate_core_freq(msr_t pstate_def) uint32_t get_pstate_core_power(msr_t pstate_def) { uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; + union pstate_msr pstate_reg; + + pstate_reg.raw = pstate_def.raw; /* Core voltage ID */ - core_vid = - (pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT; + core_vid = pstate_reg.cpu_vid_0_7 | pstate_reg.cpu_vid_8 << 8; /* Current value in amps */ - current_value_amps = - (pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT; + current_value_amps = pstate_reg.idd_value; /* Current divisor */ - current_divisor = - (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; + current_divisor = pstate_reg.idd_div; /* Voltage */ if (core_vid == 0x00) { diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 30ac560c3b..8ac48bfd36 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -6,19 +6,23 @@ #define AMD_PHOENIX_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 -#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) -#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 -#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT) -#define PSTATE_DEF_LO_CORE_VID_SHIFT 14 -#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT) -#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8 -#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT) +union pstate_msr { + struct { + uint64_t cpu_fid_0_7 : 8; /* [ 0.. 7] */ + uint64_t cpu_dfs_id : 6; /* [ 8..13] */ + uint64_t cpu_vid_0_7 : 8; /* [14..21] */ + uint64_t idd_value : 8; /* [22..29] */ + uint64_t idd_div : 2; /* [30..31] */ + uint64_t cpu_vid_8 : 1; /* [32..32] */ + uint64_t : 30; /* [33..62] */ + uint64_t pstate_en : 1; /* [63..63] */ + }; + uint64_t raw; +}; + #define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8 #define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A #define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0 -#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ |