soc/amd/*/data_fabric: Move register offsets to soc

Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.

Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 9 insertions, 4 deletions

diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h
index 32cbd20930..7be4b15b1f 100644
--- a/src/soc/amd/glinda/include/soc/data_fabric.h
+++ b/src/soc/amd/glinda/include/soc/data_fabric.h
@@ -1,14 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Glinda */
-
 #ifndef AMD_GLINDA_DATA_FABRIC_H
 #define AMD_GLINDA_DATA_FABRIC_H
 
 #include <types.h>
 
-/* SoC-specific bits in D18F0_MMIO_CTRL0 */
-#define   DF_MMIO_NP			BIT(3)
+/* D18F0 - Fabric Configuration registers */
+#define D18F0_MMIO_BASE0		0xD80
+#define D18F0_MMIO_LIMIT0		0xD84
+#define   D18F0_MMIO_SHIFT		16
+#define D18F0_MMIO_CTRL0		0xD88
+
+#define DF_FICAA_BIOS			0x8C
+#define DF_FICAD_LO			0xB8
+#define DF_FICAD_HI			0xBC
 
 #define IOMS0_FABRIC_ID			15