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authorFelix Held <felix-coreboot@felixheld.de>2023-03-23 19:25:20 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-24 23:16:41 +0000
commit6a6d524b0a6383dd054a2e810c24789b5a033b16 (patch)
treed0a2af4fbd0f6788631a07a9aa632ce74d1e8081 /src/soc/amd/glinda/fw.cfg
parentff23f455c4affde98926c7a12d62ede4781b72b5 (diff)
soc/amd/mendocino: add and use missing cpu_vid_8 pstate_msr field
Mendocino uses the SVI3 standard for CPU core voltage control which uses 9 data bits instead of the 8 in the SVI2 case and also calculates the actual voltages with a different formula. The Mendocino code uses the correct formula since commit 8d2bfbce23f6 ("soc/amd/sabrina/acpi: Correct VID decoding on Sabrina"), but the MSR definition in the PPR hasn't been updated to show the additional bit. The definition of the register that is mirrored by these MSRs descries this 9th CPU voltage ID bit though. Since this bit is expected to be zero, this shouldn't cause a change in behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I05acd239300836a34e40cd3f31ea819b79766e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73969 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/glinda/fw.cfg')
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