summaryrefslogtreecommitdiff
path: root/src/soc/amd/glinda/fch.c
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2024-08-07 16:39:36 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-08-08 17:42:05 +0000
commitab7410a4d00c3c236b14c7ecb23822fc2c7939d8 (patch)
treebdc8cf415d7d72aafb4d1ae4abd685089255850d /src/soc/amd/glinda/fch.c
parentbcc9ad50f91db278fa11e408ba5ac575437b10bb (diff)
soc/amd/*: pass PSP NVRAM base and size to amdfwtool
Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa which doesn't use/support this. This was previously only implemented for Picasso, but not for the SoCs that support this, so add the support to those other SoCs as well. If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the start and length of it in the flash will be passed to amdfwtool which then adds the base and length to the corresponding type 0x04 PSP directory table entry. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/83814 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/glinda/fch.c')
0 files changed, 0 insertions, 0 deletions