soc/amd: Use common reset code for PHX & Glinda SoCs

This switches the Phoenix & Glinda SoCs to use the common reset code.

Cezanne and newer do not support warm reset, so use cold resets in all
cases (including the OS).

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 4 deletions

diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc
index 891a68dadd..ef0d27dd3e 100644
--- a/src/soc/amd/glinda/Makefile.inc
+++ b/src/soc/amd/glinda/Makefile.inc
@@ -15,19 +15,16 @@ bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
 bootblock-y	+= i2c.c
-bootblock-y	+= reset.c
 bootblock-y	+= uart.c
 
 verstage-y	+= i2c.c
 verstage-y	+= espi_util.c
 verstage_x86-y	+= gpio.c
-verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c
 
 romstage-y	+= fsp_m_params.c
 romstage-y	+= gpio.c
 romstage-y	+= i2c.c
-romstage-y	+= reset.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
@@ -40,7 +37,6 @@ ramstage-y	+= fsp_s_params.c
 ramstage-y	+= gpio.c
 ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
-ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
 ramstage-y	+= xhci.c