diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-13 14:34:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-10 16:01:20 +0000 |
| commit | c666a916112aece345da57a0b4f3bafc43234ee7 (patch) | |
| tree | 59cfab421bd92ff5635aa651a9062779bc0d3fbf /src/soc/amd/genoa/include | |
| parent | 4da9d6b41d08e58e0e8a868acd76cedfb1b54586 (diff) | |
soc/amd/genoa: Enable eSPI early
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/genoa/include')
| -rw-r--r-- | src/soc/amd/genoa/include/soc/acpi.h | 8 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/lpc.h | 16 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/pci_devs.h | 48 |
3 files changed, 72 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/include/soc/acpi.h b/src/soc/amd/genoa/include/soc/acpi.h new file mode 100644 index 0000000000..51fa91ef93 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/acpi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_GENOA_ACPI_H +#define AMD_GENOA_ACPI_H + +#define ACPI_SCI_IRQ 9 + +#endif /* AMD_GENOA_ACPI_H */ diff --git a/src/soc/amd/genoa/include/soc/lpc.h b/src/soc/amd/genoa/include/soc/lpc.h new file mode 100644 index 0000000000..f98ffe8ef8 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/lpc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_LPC_H +#define AMD_GENOA_LPC_H + +#define SPI_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_GENOA_LPC_H */ diff --git a/src/soc/amd/genoa/include/soc/pci_devs.h b/src/soc/amd/genoa/include/soc/pci_devs.h new file mode 100644 index 0000000000..d314deb4a5 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/pci_devs.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_PCI_DEVS_H +#define AMD_GENOA_PCI_DEVS_H + +#include <device/pci_def.h> +#include <amdblocks/pci_devs.h> + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + +#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7) +#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7) + +#endif |