soc/amd/genoa: add PCI domain resource reporting

Use the common AMD data fabric resource reporting code to report how
openSIL distributed PCI buses, MMIO, and IO resources to coreboot's
resource allocator. This replaces the original CB:76521 which was
written back when the common AMD data fabric resource reporting code
didn't exist yet.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifcd655ea6d5565668ffee36d0d022b2b711c0b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>

1 files changed, 41 insertions, 0 deletions

diff --git a/src/soc/amd/genoa/domain.c b/src/soc/amd/genoa/domain.c
new file mode 100644
index 0000000000..43e436a00a
--- /dev/null
+++ b/src/soc/amd/genoa/domain.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/data_fabric.h>
+#include <amdblocks/root_complex.h>
+#include <amdblocks/smn.h>
+#include <arch/ioapic.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <types.h>
+
+#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
+
+static void genoa_domain_set_resources(struct device *domain)
+{
+	if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+		printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
+		       domain->path.domain.domain);
+		const union df_vga_en vga_en = {
+			.ve = 1,
+			.dst_fabric_id = get_iohc_fabric_id(domain),
+		};
+		data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw);
+	}
+
+	pci_domain_set_resources(domain);
+
+	/* Enable IOAPIC memory decoding */
+	struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+	if (res) {
+		const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain);
+		uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO);
+		ioapic_base |= (1 << 0);
+		smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base);
+	}
+}
+
+struct device_operations genoa_pci_domain_ops = {
+	.read_resources	  = amd_pci_domain_read_resources,
+	.set_resources	  = genoa_domain_set_resources,
+	.scan_bus	  = amd_pci_domain_scan_bus,
+};