diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-14 20:08:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-11 11:04:36 +0000 |
| commit | 663c57731185dcd25436f9ba8ebf4550d6ad4ae7 (patch) | |
| tree | db963c40a19274ef763c31a61012e0f87f091813 /src/soc/amd/genoa/chipset.cb | |
| parent | 543c1ee31497f97337e6e955334fc08da673b6e8 (diff) | |
soc/amd/genoa: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.
Add USB OC pins to chipset.cb
In the process of scrubbing opensil for public release USB became non
functional.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/amd/genoa/chipset.cb')
| -rw-r--r-- | src/soc/amd/genoa/chipset.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 60918e9bf1..83a708255d 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -3,6 +3,12 @@ chip soc/amd/genoa device cpu_cluster 0 on ops amd_cpu_bus_ops end + # OC pins + register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }" + register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }" + device domain 0 on ops genoa_pci_domain_ops device pci 00.0 alias gnb_0 on end |