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authorvbpandya <pandyavarshit@gmail.com>2023-09-22 20:49:37 +0530
committerFelix Held <felix-coreboot@felixheld.de>2023-09-28 13:37:56 +0000
commit87d8b8cff0ec36b0cd2a596d1639a90756d91882 (patch)
tree4882d833ed5ec06833c2c30df2541c25c2acf945 /src/soc/amd/genoa/Kconfig
parentf1bf2d919044902d60b1a36eba16feba4a6c8b3d (diff)
soc/amd/genoa: Add chipset.cb
Change-Id: I6c9879a9f06f81d577bc09f6001158d7f9326362 Signed-off-by: vbpandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78082 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/genoa/Kconfig')
-rw-r--r--src/soc/amd/genoa/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index f799ac18a2..0331e36518 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -19,6 +19,10 @@ config SOC_SPECIFIC_OPTIONS
config USE_EXP_X86_64_SUPPORT
default y
+config CHIPSET_DEVICETREE
+ string
+ default "soc/amd/genoa/chipset.cb"
+
config EARLY_RESERVED_DRAM_BASE
hex
default 0x7000000