device/device.h: Rename busses for clarity

This renames bus to upstream and link_list to downstream.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

3 files changed, 36 insertions, 37 deletions

diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 57b5974e71..bd52d7ca6f 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -96,7 +96,7 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
 		memset(ivhd_entry, 0, sizeof(*ivhd_entry));
 
 		ivhd_entry->type = type;
-		ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
+		ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
 		ivhd_entry->dte_setting = data;
 		*current += sizeof(ivrs_ivhd_generic_t);
 	} else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) {
@@ -104,12 +104,12 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
 		memset(ivhd_entry, 0, sizeof(*ivhd_entry));
 
 		ivhd_entry->type = type;
-		ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
+		ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
 		ivhd_entry->dte_setting = data;
 		ivhd_entry->reserved1 = 0;
 		ivhd_entry->reserved2 = 0;
 		ivhd_entry->source_dev_id = parent->path.pci.devfn |
-					    (parent->bus->secondary << 8);
+					    (parent->upstream->secondary << 8);
 		*current += sizeof(ivrs_ivhd_alias_t);
 	}
 
@@ -145,7 +145,7 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
 		return;
 
 	if (dev->path.type == DEVICE_PATH_PCI) {
-		if ((dev->bus->secondary == nb_bus) &&
+		if ((dev->upstream->secondary == nb_bus) &&
 		    (dev->path.pci.devfn == 0x0))
 			*root_level = depth;
 
@@ -154,9 +154,9 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
 				ivrs_add_device_or_bridge(parent, dev, current);
 	}
 
-	if (!dev->link_list)
+	if (!dev->downstream)
 		return;
-	for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling)
+	for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling)
 		add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current,
 					nb_bus);
 }
@@ -173,21 +173,21 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev)
 	 * Add all possible PCI devices in the domain that can generate transactions
 	 * processed by IOMMU. Start with device <bus>:01.0
 	*/
-	current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->link_list->secondary << 8),
-				 0xff | (dev->link_list->subordinate << 8), 0);
+	current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->downstream->secondary << 8),
+				 0xff | (dev->downstream->subordinate << 8), 0);
 
 	add_ivhd_device_entries(NULL, dev, 0, -1, &root_level,
-		&current, dev->link_list->secondary);
+		&current, dev->downstream->secondary);
 
 	res = probe_resource(dev, IOMMU_IOAPIC_IDX);
 	if (res) {
 		/* Describe IOAPIC associated with the IOMMU */
 		current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base,
-				      PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0);
+				      PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0);
 	}
 
 	/* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */
-	if (dev->link_list->secondary == 0) {
+	if (dev->downstream->secondary == 0) {
 		/* Describe HPET */
 		current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN);
 		/* Describe FCH IOAPICs */
@@ -212,11 +212,11 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i
 	ivhd_40->flags = ivhd->flags & 0x3f;
 	ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40);
 	/* BDF <bus>:00.2 */
-	ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8);
+	ivhd_40->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
 	ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
 	ivhd_40->iommu_base_low = ivhd->iommu_base_low;
 	ivhd_40->iommu_base_high = ivhd->iommu_base_high;
-	ivhd_40->pci_segment_group = nb_dev->bus->segment_group;
+	ivhd_40->pci_segment_group = nb_dev->upstream->segment_group;
 	ivhd_40->iommu_info = ivhd->iommu_info;
 	/* For type 40h bits 31:28 and 12:0 are reserved */
 	ivhd_40->iommu_attributes = ivhd->iommu_feature_info & 0xfffe000;
@@ -230,9 +230,9 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i
 
 	/* Now repeat all the device entries from type 10h */
 	current_backup = current;
-	current = acpi_ivhd_misc(current, nb_dev->bus->dev);
+	current = acpi_ivhd_misc(current, nb_dev->upstream->dev);
 
-	if (nb_dev->bus->secondary == 0) {
+	if (nb_dev->upstream->secondary == 0) {
 		/* Describe EMMC */
 		if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) {
 			/* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the
@@ -269,11 +269,11 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i
 	ivhd_11->flags = ivhd->flags & 0x3f;
 	ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11);
 	/* BDF <bus>:00.2 */
-	ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8);
+	ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
 	ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
 	ivhd_11->iommu_base_low = ivhd->iommu_base_low;
 	ivhd_11->iommu_base_high = ivhd->iommu_base_high;
-	ivhd_11->pci_segment_group = nb_dev->bus->segment_group;
+	ivhd_11->pci_segment_group = nb_dev->upstream->segment_group;
 	ivhd_11->iommu_info = ivhd->iommu_info;
 	ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivhd->iommu_feature_info;
 	ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters;
@@ -289,7 +289,7 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i
 
 	/* Now repeat all the device entries from type 10h */
 	current_backup = current;
-	current = acpi_ivhd_misc(current, nb_dev->bus->dev);
+	current = acpi_ivhd_misc(current, nb_dev->upstream->dev);
 	ivhd_11->length += (current - current_backup);
 
 	return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev);
@@ -317,8 +317,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 
 	while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) {
 
-		nb_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
-		iommu_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 2));
+		nb_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0));
+		iommu_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 2));
 		if (!nb_dev) {
 			printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__);
 			printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__);
@@ -334,7 +334,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 		ivhd->length = sizeof(struct acpi_ivrs_ivhd);
 
 		/* BDF <bus>:00.2 */
-		ivhd->device_id = 0x02 | (nb_dev->bus->secondary << 8);
+		ivhd->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
 		ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
 		ivhd->iommu_base_low = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_LO) & 0xffffc000;
 		ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI);
@@ -363,7 +363,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
 		ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ?
 							IVHD_FLAG_HT_TUN_EN : 0);
 
-		ivhd->pci_segment_group = nb_dev->bus->segment_group;
+		ivhd->pci_segment_group = nb_dev->upstream->segment_group;
 
 		ivhd->iommu_info = pci_read_config16(iommu_dev,
 			ivhd->capability_offset + 0x10) & 0x1F;
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index b827dd3fad..f17346fedf 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -34,12 +34,12 @@ void amd_pci_domain_scan_bus(struct device *domain)
 	limit = MIN(limit, PCI_BUSES_PER_SEGMENT_GROUP - 1);
 
 	/* Set bus first number of PCI root */
-	domain->link_list->secondary = bus;
+	domain->downstream->secondary = bus;
 	/* subordinate needs to be the same as secondary before pci_host_bridge_scan_bus call. */
-	domain->link_list->subordinate = bus;
+	domain->downstream->subordinate = bus;
 	/* Tell allocator about maximum PCI bus number in domain */
-	domain->link_list->max_subordinate = limit;
-	domain->link_list->segment_group = segment_group;
+	domain->downstream->max_subordinate = limit;
+	domain->downstream->segment_group = segment_group;
 
 	pci_host_bridge_scan_bus(domain);
 }
@@ -249,12 +249,12 @@ void amd_pci_domain_fill_ssdt(const struct device *domain)
 
 	/* PCI bus number range in domain */
 	printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n",
-	       acpi_device_name(domain), domain->link_list->secondary,
-	       domain->link_list->max_subordinate, domain->link_list->segment_group);
-	acpigen_resource_producer_bus_number(domain->link_list->secondary,
-					     domain->link_list->max_subordinate);
+	       acpi_device_name(domain), domain->downstream->secondary,
+	       domain->downstream->max_subordinate, domain->downstream->segment_group);
+	acpigen_resource_producer_bus_number(domain->downstream->secondary,
+					     domain->downstream->max_subordinate);
 
-	if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) {
+	if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) {
 		/* ACPI 6.4.2.5 I/O Port Descriptor */
 		acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1,
 				   PCI_IO_CONFIG_PORT_COUNT, 1);
@@ -282,7 +282,7 @@ void amd_pci_domain_fill_ssdt(const struct device *domain)
 		}
 	}
 
-	if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+	if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 		printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain));
 		acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT,
 			MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE);
@@ -290,9 +290,8 @@ void amd_pci_domain_fill_ssdt(const struct device *domain)
 
 	acpigen_write_resourcetemplate_footer();
 
-	acpigen_write_SEG(domain->link_list->segment_group);
-	acpigen_write_BBN(domain->link_list->secondary);
-
+	acpigen_write_SEG(domain->downstream->segment_group);
+	acpigen_write_BBN(domain->downstream->secondary);
 	/* Scope */
 	acpigen_pop_len();
 }
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index c076361080..a90fc3e65c 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -280,10 +280,10 @@ static void lpc_enable_children_resources(struct device *dev)
 {
 	struct device *child;
 
-	if (!dev->link_list)
+	if (!dev->downstream)
 		return;
 
-	for (child = dev->link_list->children; child; child = child->sibling) {
+	for (child = dev->downstream->children; child; child = child->sibling) {
 		if (!child->enabled)
 			continue;
 		if (child->path.type != DEVICE_PATH_PNP)