diff options
author | Raul E Rangel <rrangel@chromium.org> | 2021-05-10 14:49:55 -0600 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-12 00:44:17 +0000 |
commit | e4f831786c7b636830f8092bca07fb19b79978a9 (patch) | |
tree | 055f7b4838fb1a58e30484f5fe4875ef4dda590e /src/soc/amd/common/block | |
parent | 8479656c7194878ff893212ff4a949947e1f290e (diff) |
soc/amd{common,cezanne}: Move pcie_gpp.c to common
Cezanne and Picasso can now use the same driver.
BUG=b:184766519
TEST=Boot guybrush and dump ASL. Verified it didn't change.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block')
-rw-r--r-- | src/soc/amd/common/block/pci/Kconfig | 6 | ||||
-rw-r--r-- | src/soc/amd/common/block/pci/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/amd/common/block/pci/pcie_gpp.c | 88 |
3 files changed, 95 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 4af0aa0d64..302a6b8497 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -10,3 +10,9 @@ config SOC_AMD_COMMON_BLOCK_PCI_MMCONF help Selecting this option adds the AMD-common enable_pci_mmconf function to the build. + +config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER + bool + depends on SOC_AMD_COMMON_BLOCK_PCI + help + Select this option to use AMD common PCIe GPP driver. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 8c7a9899ae..e013777acc 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) ramstage-y += amd_pci_util.c ramstage-y += pci_routing_info.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c new file mode 100644 index 0000000000..58c776146f --- /dev/null +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <amdblocks/amd_pci_util.h> +#include <assert.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pciexp.h> +#include <soc/pci_devs.h> +#include <stdio.h> +#include <stdlib.h> + +static const char *pcie_gpp_acpi_name(const struct device *dev) +{ + char *name; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + name = malloc(ACPI_NAME_BUFFER_SIZE); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "GP%02x", dev->path.pci.devfn); + name[4] = '\0'; + + return name; +} + +static void acpi_device_write_gpp_pci_dev(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + assert(dev->path.type == DEVICE_PATH_PCI); + assert(name); + assert(scope); + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_ADR_pci_device(dev); + acpigen_write_STA(acpi_device_status(dev)); + + acpigen_write_pci_GNB_PRT(dev); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static struct device_operations internal_pcie_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, +}; + +static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { + .ops = &internal_pcie_gpp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, +}; + +static struct device_operations external_pcie_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, +}; + +static const unsigned short external_pci_gpp_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2, + 0 +}; + +static const struct pci_driver external_pcie_gpp_driver __pci_driver = { + .ops = &external_pcie_gpp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = external_pci_gpp_ids, +}; |