soc/amd: factor out non-CAR romstage to common code

Since the romstage code is very similar between all AMD non-CAR SoCs,
factor out a common romstage implementation. All SoCs that select
SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so
this Kconfig option can be used to determine whether to make that call.
In the FSP case, amd_fsp_early_init gets called, while in the case of an
implementation that doesn't rely on an FSP to do the initialization,
cbmem_initialize_empty gets called to set up CBMEM which otherwise would
be done inside the FSP driver code. Since only some SoCs call
fch_disable_legacy_dma_io again in romstage right after
amd_fsp_early_init, introduce the new
SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the
SoCs can specify if this call is needed or not.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

3 files changed, 46 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 1ffaece9dd..3dc90ac3b2 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -38,6 +38,12 @@ config ACPI_CPU_STRING
 	string
 	default "C%03X"
 
+config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
+	bool
+	help
+	  Disable the legacy DMA decodes again after the call into the
+	  reference code in romstage to fix up things.
+
 endif # SOC_AMD_COMMON_BLOCK_NONCAR
 
 config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index f8ca357c40..f3ada6250f 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -8,6 +8,7 @@ bootblock-y += pre_c.S
 bootblock-y += write_resume_eip.c
 bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c
 romstage-y += memmap.c
+romstage-y += romstage.c
 ramstage-y += cpu.c
 romstage-y += cpu.c
 ramstage-y += memmap.c
diff --git a/src/soc/amd/common/block/cpu/noncar/romstage.c b/src/soc/amd/common/block/cpu/noncar/romstage.c
new file mode 100644
index 0000000000..1ce692d568
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/romstage.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
+#include <amdblocks/post_codes.h>
+#include <amdblocks/memmap.h>
+#include <amdblocks/pmlib.h>
+#include <amdblocks/stb.h>
+#include <cbmem.h>
+#include <program_loading.h>
+#include <romstage_common.h>
+
+void __noreturn romstage_main(void)
+{
+	post_code(POSTCODE_ROMSTAGE_MAIN);
+
+	if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE))
+		write_stb_to_console();
+
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE)) {
+		/* Snapshot chipset state prior to any reference code call. */
+		fill_chipset_state();
+	}
+
+	if (CONFIG(PLATFORM_USES_FSP2_0)) {
+		amd_fsp_early_init();
+	} else {
+		cbmem_initialize_empty();
+	}
+
+	if (CONFIG(SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP)) {
+		/* Fix up settings the reference code should not be changing */
+		fch_disable_legacy_dma_io();
+	}
+
+	memmap_stash_early_dram_usage();
+
+	run_ramstage();
+}