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authorRaul E Rangel <rrangel@chromium.org>2021-05-24 13:02:40 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-05-26 11:37:32 +0000
commit8fef0b7010490c8cb21e32ed5ce66f40dae1e0a9 (patch)
tree2849155fc6b0bbc2c1c598aec1f9b65584ef1ae0 /src/soc/amd/common/block
parent4a2887f38132df7ee55286564a11cd1e6e578db2 (diff)
soc/amd/common/block/espi: Fix typo in espi_setup_periph_channel
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective. It is set when the eSPI peripheral has configured the channel. We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never caused an issue before because the peripheral channel is enabled by default after PLTRST# is deasserted. This does fix the case where periph_ch_en == 0. It now properly clears the enable flag. BUG=b:188188172, b:188935533 TEST=Boot guybrush to OS, perform warm reset Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/common/block')
-rw-r--r--src/soc/amd/common/block/lpc/espi_util.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0ea014fee2..e6ae2cb505 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -838,8 +838,8 @@ static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t
{
uint32_t slave_config;
/* Peripheral channel requires BME bit to be set when enabling the channel. */
- const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_READY |
- ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE;
+ const uint32_t slave_en_mask =
+ ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE;
if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1)
return -1;