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authorMartin Roth <gaumless@gmail.com>2023-02-01 11:55:28 -0700
committerFelix Held <felix-coreboot@felixheld.de>2023-02-04 03:22:50 +0000
commitc46c15b5920bf8378c333f862a8f5766cf104c85 (patch)
treee867fe9aff8e07265ec614d8645d30031a935996 /src/soc/amd/common/block/include
parent9f5a5eefc32b6db7418955968f888ba3fccab3c7 (diff)
soc/amd: Create AMD common reset code
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/include')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/reset.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h
index 353720c1e0..3706d08d6b 100644
--- a/src/soc/amd/common/block/include/amdblocks/reset.h
+++ b/src/soc/amd/common/block/include/amdblocks/reset.h
@@ -3,9 +3,11 @@
#ifndef AMD_BLOCK_RESET_H
#define AMD_BLOCK_RESET_H
-#include <console/console.h>
+#include <amdblocks/acpimmio.h>
#include <arch/cache.h>
+#include <console/console.h>
#include <halt.h>
+#include <soc/southbridge.h>
void do_warm_reset(void);
void do_cold_reset(void);
@@ -28,4 +30,10 @@ static inline __noreturn void cold_reset(void)
halt();
}
+static inline void set_resets_to_cold(void)
+{
+ /* De-assert and then assert all PwrGood signals on CF9 reset. */
+ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
+}
+
#endif /* AMD_BLOCK_RESET_H */