diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-24 10:41:37 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 18:44:41 +0000 |
| commit | 29b7f1459d709155045befb156fea00a2efd79b0 (patch) | |
| tree | 7c14492d87e507cfbb2ca780603fd4176707a562 /src/soc/amd/common/block/include/amdblocks | |
| parent | 18456169e63f5b6f5f4ce34f40a047ce51b7a1f6 (diff) | |
soc/amd/common/block/include/gpio_defs: rework de-glitching defines
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/gpio_defs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 0422079421..1e3b172dd7 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -105,10 +105,10 @@ #define DEB_GLITCH_SHIFT 5 #define DEB_GLITCH_LOW 1 #define DEB_GLITCH_HIGH 2 -#define DEB_GLITCH_NONE 3 +#define DEB_GLITCH_REMOVE 3 #define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) #define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) -#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) +#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT) #define GPIO_TIMEBASE_61uS 0 #define GPIO_TIMEBASE_183uS (1 << 4) |