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authorRaul E Rangel <rrangel@chromium.org>2021-07-23 14:53:05 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-10-20 15:49:23 +0000
commita76e64709491664765e33b55826e5af87c1f20ce (patch)
tree62c5555654b19109bac6eee6daeb865cce979dc4 /src/soc/amd/common/block/cpu/noncar
parentfbf874fb381af8a0ef2c058538919d133e630d4d (diff)
soc/amd/common/block/cpu: Remove magic number in memlayout
The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/common/block/cpu/noncar')
-rw-r--r--src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 59631f3ada..005bde093b 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -103,8 +103,8 @@ SECTIONS
* the payload on non-S3 boots, so we don't need to reserve it from the
* OS. The 64 byte alignment is required by the SPI DMA controller.
*/
- . = ALIGN(64);
- REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64)
+ . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
+ REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE)
#endif
RAMSTAGE(CONFIG_RAMBASE, 8M)