lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload

Now that CBFS has this functionality built in, we no longer need to
manually code it.

payload_preload used to use the payload_preload_cache region to store
the raw payload contents. This region was placed outside the firmware
reserved region, so it was available for use by the OS. This was
possible because the payload isn't loaded again on S3 resume.

cbfs_preload only uses the cbfs_cache region. This region must be
reserved because it gets used on the S3 resume path. Unfortunately this
means that cbfs_cache must be increased to hold the payload. Cezanne is
the only platform currently using payload_preload, and the size of
cbfs_cache has already been adjusted.

In the future we could look into adding an option to cbfs_preload that
would allow it to use a different memory pool for the cache allocation.

BUG=b:179699789
TEST=Boot guybrush and verify preloading the payload was successful
CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

1 files changed, 0 insertions, 10 deletions

diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index a542b7d6ad..e42174f765 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -106,16 +106,6 @@ SECTIONS
 
 	EARLY_RESERVED_DRAM_END(.)
 
-#if CONFIG(PAYLOAD_PRELOAD)
-        /*
-         * This section is outside the early_reserved_dram section. We only read
-         * the payload on non-S3 boots, so we don't need to reserve it from the
-         * OS. The 64 byte alignment is required by the SPI DMA controller.
-         */
-        . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
-        REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE)
-#endif
-
 	RAMSTAGE(CONFIG_RAMBASE, 8M)
 }