soc/amd/cezanne,glinda,mendocino,phoenix,picasso/Kconfig: use all target

The i2c.c compilation unit is added to all stages in all cases, so use
the all target instead of adding it to all stages separately. Also order
the all targets alphabetically.

TEST=Timeless build on Mandolin results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie90380075a3c87d226cdcb0f41f7e94275eaaa42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

1 files changed, 2 insertions, 5 deletions

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index c21e219bd6..bf5769836c 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -5,22 +5,20 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
 # Beware that all-y also adds the compilation unit to verstage on PSP
-all-y		+= config.c
 all-y		+= aoac.c
+all-y		+= config.c
+all-y		+= i2c.c
 
 bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
-bootblock-y	+= i2c.c
 bootblock-y	+= uart.c
 
-verstage-y	+= i2c.c
 verstage_x86-y	+= gpio.c
 verstage_x86-y	+= uart.c
 
 romstage-y	+= fsp_m_params.c
 romstage-y	+= gpio.c
-romstage-y	+= i2c.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
@@ -32,7 +30,6 @@ ramstage-y	+= fch.c
 ramstage-y	+= fsp_s_params.c
 ramstage-y	+= gpio.c
 ramstage-y	+= graphics.c
-ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c