diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-23 23:05:50 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 23:17:02 +0000 |
| commit | 3f2844fb1ee51b879dee9824d53924ca7c3f5cff (patch) | |
| tree | 695506bf7152be46191dc544a20c549dfe48528c /src/soc/amd/cezanne | |
| parent | 6a6d524b0a6383dd054a2e810c24789b5a033b16 (diff) | |
soc/amd/*/include/msr: add version number to SERIAL_VID_* define names
Picasso and Cezanne use the serial voltage ID 2 standard to communicate
the CPU voltage to the voltage regulator module on the mainboard, while
Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for
this. Both standards encode the voltage in a different way, so add the
serial VID version number to the defines to clarify for which version
the define is.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index f65973d979..43ed7fed05 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -150,8 +150,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) /* Voltage off for VID codes 0xF8 to 0xFF */ voltage_in_uvolts = 0; } else { - voltage_in_uvolts = - SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); + voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS - + (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); } /* Power in mW */ diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 2ce03ade8a..fdbe47e342 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -23,8 +23,8 @@ union pstate_msr { #define PSTATE_DEF_CORE_FREQ_BASE 25 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_MAX_MICROVOLTS 1550000L +#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 |