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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-08-05 21:38:59 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-22 19:42:05 +0000 |
| commit | 348f2a63707cc1711cc836837fc7f5b36b2e0553 (patch) | |
| tree | b69fec1b9623d3e3ab221d5e4523848b0ebad40e /src/soc/amd/cezanne/i2c.c | |
| parent | 6e64c1a4e09de71d359c3123f7be1dfceba1f0a1 (diff) | |
soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP init
FSP takes care of setting the MSR LT_LOCK_MEMORY when SkipMpInit=0.
Thus, only set the lock when native MP init is used (SkipMpInit=1).
Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/i2c.c')
0 files changed, 0 insertions, 0 deletions