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authorFelix Held <felix-coreboot@felixheld.de>2021-02-13 02:36:02 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-06-01 20:37:04 +0000
commitc4eb45fa85d9860ce94829c6c977b9e28a297bf9 (patch)
tree4b1f29ce8cf52e878ee54e16127f685e53ac7f31 /src/soc/amd/cezanne/cpu.c
parentdb4b21a1d04678041fae73be4a700f393cee879d (diff)
soc/amd/picasso: introduce and use chipset device tree
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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