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authorFelix Held <felix-coreboot@felixheld.de>2023-06-01 22:01:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-07 18:53:57 +0000
commit90044bd6d14e1a11a056db34e38ab4f150351990 (patch)
tree61100faeb85d063cb8c41261890bb5ef9627c19c /src/soc/amd/cezanne/acpi/soc.asl
parent15aa0a56ce751f7c36402fe74b6bc3c636c26307 (diff)
soc/amd/cezanne/acpi: use ROOT_BRIDGE macro
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75592 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/acpi/soc.asl')
-rw-r--r--src/soc/amd/cezanne/acpi/soc.asl7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index f8f7a8a7a8..4ab03d0f36 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <soc/amd/common/acpi/pci_root.asl>
#include "globalnvs.asl"
Scope(\_SB) {
@@ -16,7 +17,11 @@ Scope(\_SB) {
#include "mmio.asl"
- #include "pci0.asl"
+ ROOT_BRIDGE(PCI0)
+
+ Scope(PCI0) {
+ #include <soc/amd/common/acpi/lpc.asl>
+ } /* End PCI0 scope */
} /* End \_SB scope */
#include <soc/amd/common/acpi/alib.asl>