diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2022-02-01 11:12:33 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-02 23:31:51 +0000 |
| commit | fa4d0510ea4952829114ff7ca877749bed049094 (patch) | |
| tree | eb5e832188897ff41c4e4d9e1600a6ddceea145e /src/soc/amd/cezanne/Kconfig | |
| parent | 21fdd44db037e4751f9793a2fcf4a3646a70fd88 (diff) | |
soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.
BUG=b:215425753
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index f2fdc7fc08..620c650ba1 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -342,13 +342,11 @@ config PSP_DISABLE_POSTCODES help Disables the output of port80 post codes from PSP. -config PSP_POSTCODES_ON_ESPI - bool "Use eSPI bus for PSP post codes" - default y - depends on !PSP_DISABLE_POSTCODES +config PSP_INIT_ESPI + bool "Initialize eSPI in PSP Stage 2 Boot Loader" help - Select to send PSP port80 post codes on eSPI bus. - If not selected, PSP port80 codes will be sent on LPC bus. + Select to initialize the eSPI controller in the PSP Stage 2 Boot + Loader. config PSP_LOAD_MP2_FW bool |