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authorFelix Held <felix.held@amd.corp-partner.google.com>2021-10-22 22:38:21 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-10-26 15:37:45 +0000
commit3a79633920850cb1d44f515a9cfe8372c6c01341 (patch)
treeaef9b03b2e808647c97d8173d5d77cd1e7e6d334 /src/security/Makefile.inc
parentcb2fd20c7f5cf43776dddfe2dbafeb19475e81f3 (diff)
soc/*/Makefile: don't add cpu/x86/cache
No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/security/Makefile.inc')
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