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authorPatrick Rudolph <patrick.rudolph@9elements.com>2023-12-21 14:45:27 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-04-07 12:04:03 +0000
commite27a26bdefdee6fda89dbd8228cc123dfd95859e (patch)
tree3d1e2246e27b37118109099493eb9b796c0e78b3 /src/northbridge
parent8f14e8e6b25e04df5d5b03e38be54eda8eff1f81 (diff)
nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.bin
A register dump between native and MRC.bin raminit showed a difference in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses. Tested on Lenovo X220: Still boots and works fine. Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79759 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 2e4967532e..3f5e290c57 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -2833,7 +2833,10 @@ void final_registers(ramctr_timing *ctrl)
}
mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff);
- mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay);
+ if (IS_SANDY_CPU(ctrl->cpu))
+ mchbar_write32(PM_DLL_CONFIG, 0x000330f0);
+ else
+ mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay);
FOR_ALL_CHANNELS {
switch (ctrl->rankmap[channel]) {