CBMEM: Unify get_top_of_ram()

Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>

11 files changed, 6 insertions, 10 deletions

diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
index fd62184040..25075bd69d 100644
--- a/src/northbridge/amd/lx/northbridge.h
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -28,7 +28,6 @@ int sizeram(void);
 
 /* northbridgeinit.c */
 void northbridge_init_early(void);
-uint32_t get_top_of_ram(void);
 
 /* pll_reset.c */
 unsigned int GeodeLinkSpeed(void);
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 3768777187..f4c13f752f 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
+#include <cbmem.h>
 
 struct gliutable {
 	unsigned long desc_name;
@@ -713,7 +714,7 @@ static void setup_lx_cache(void)
 	wbinvd();
 }
 
-uint32_t get_top_of_ram(void)
+unsigned long get_top_of_ram(void)
 {
 	struct gliutable *gl = 0;
 	uint32_t systop;
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index ae02a7c3d0..3d4dfe2624 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -25,6 +25,7 @@
 #include <assert.h>
 #include <spd.h>
 #include <sdram_mode.h>
+#include <cbmem.h>
 
 #include "raminit.h"
 #include "e7505.h"
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h
index f9ba7968be..8eb4990364 100644
--- a/src/northbridge/intel/e7505/raminit.h
+++ b/src/northbridge/intel/e7505/raminit.h
@@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr);
 void e7505_mch_done(const struct mem_controller *memctrl);
 int e7505_mch_is_ready(void);
 
-unsigned long get_top_of_ram(void);
 
 /* Mainboard exports this. */
 int spd_read_byte(unsigned device, unsigned address);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 2dffcad0fc..227baef082 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -422,7 +422,6 @@ void gm45_late_init(stepping_t);
 
 u32 decode_igd_memory_size(u32 gms);
 u32 decode_igd_gtt_size(u32 gsm);
-u32 get_top_of_ram(void);
 
 void init_iommu(void);
 #endif
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 28e947b393..a029020748 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -26,6 +26,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
+#include <cbmem.h>
 #include "gm45.h"
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
@@ -83,7 +84,7 @@ u32 decode_igd_gtt_size(const u32 gsm)
 	}
 }
 
-u32 get_top_of_ram(void)
+unsigned long get_top_of_ram(void)
 {
 	const pci_devfn_t dev = PCI_DEV(0, 0, 0);
 
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 46be570a8a..706c286f39 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -23,7 +23,6 @@
 #include "pei_data.h"
 
 void sdram_initialize(struct pei_data *pei_data);
-unsigned long get_top_of_ram(void);
 int fixup_haswell_errata(void);
 /* save_mrc_data() must be called after cbmem has been initialized. */
 void save_mrc_data(struct pei_data *pei_data);
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 2d8ef9e595..9eb41935e2 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -69,7 +69,6 @@ struct sys_info {
 
 void receive_enable_adjust(struct sys_info *sysinfo);
 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
-unsigned long get_top_of_ram(void);
 int fixup_i945_errata(void);
 void udelay(u32 us);
 
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 4cd86cd9df..4abcec33cb 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -51,7 +51,7 @@ int bridge_silicon_revision(void)
 	return bridge_revision_id;
 }
 
-static unsigned long get_top_of_ram(void)
+unsigned long get_top_of_ram(void)
 {
 	/* Base of TSEG is top of usable DRAM */
 	u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG);
diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h
index 23bdbd9ed1..2e9b1f32f4 100644
--- a/src/northbridge/intel/sandybridge/raminit.h
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -30,7 +30,6 @@ struct sys_info {
 } __attribute__ ((packed));
 
 void sdram_initialize(struct pei_data *pei_data);
-unsigned long get_top_of_ram(void);
 int fixup_sandybridge_errata(void);
 
 #endif				/* RAMINIT_H */
diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h
index dcb24b5f75..46e30232b7 100644
--- a/src/northbridge/via/vx900/early_vx900.h
+++ b/src/northbridge/via/vx900/early_vx900.h
@@ -61,7 +61,6 @@
 #define RAMINIT_USE_HW_RXCR_CALIB	0
 #define RAMINIT_USE_HW_MRS_SEQ		0
 
-unsigned long get_top_of_ram(void);
 
 void enable_smbus(void);
 void dump_spd_data(spd_raw_data spd);