diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-14 01:44:44 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-21 02:07:02 +0000 |
| commit | 7d11513ab3281ef3bee83b4b523219b683d3ddc1 (patch) | |
| tree | 6c4a5113c88de64ce18eacdc14c1806bd69cd6ae /src/northbridge | |
| parent | 8360946c8e2b0f57d7e12eeb1df72bf2b9410e63 (diff) | |
nb/intel/sandybridge: Introduce `disable_refresh_machine` function
The same IOSAV sequence is used in both loops, so there's no need to
reprogram it again in the second loop.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 74 |
1 files changed, 23 insertions, 51 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 893d6b27de..885689c94f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1933,21 +1933,33 @@ static void train_write_flyby(ramctr_timing *ctrl) MCHBAR32(GDCRTRAININGMOD) = 0; } -static void write_op(ramctr_timing *ctrl, int channel) +static void disable_refresh_machine(ramctr_timing *ctrl) { - int slotrank; + int channel; - wait_for_iosav(channel); + FOR_ALL_POPULATED_CHANNELS { + /* choose an existing rank */ + const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); + /* Execute command queue */ + iosav_run_once(channel); - /* Execute command queue */ - iosav_run_once(channel); + wait_for_iosav(channel); - wait_for_iosav(channel); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); + } + + /* Refresh disable */ + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); + + FOR_ALL_POPULATED_CHANNELS { + /* Execute the same command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); + } } /* @@ -1970,16 +1982,7 @@ int write_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); - FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - } + disable_refresh_machine(ctrl); /* Enable write leveling on all ranks Disable all DQ outputs @@ -2142,38 +2145,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) static void reprogram_320c(ramctr_timing *ctrl) { - int channel, slotrank; - - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* Choose an existing rank */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } + disable_refresh_machine(ctrl); /* JEDEC reset */ dram_jedecreset(ctrl); |