Drop duplicated and unneeded #defines from some northbridges (trivial).

This is generic PCI stuff, not nothbridge-specific in any way.
The respective #defines are already present in src/include/device/pci_def.h.

Abuild-tested, so shouldn't break anything.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 1 insertions, 37 deletions

diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h
index be76303d4f..61401e47ae 100644
--- a/src/northbridge/intel/e7520/e7520.h
+++ b/src/northbridge/intel/e7520/e7520.h
@@ -1,8 +1,3 @@
-#define VID     0X00
-#define DID     0X02
-#define PCICMD  0X04
-#define PCISTS  0X06
-#define RID	0X08
 #define IURBASE	0X14
 #define MCHCFG0	0X50
 #define MCHSCRB	0X52
diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h
index be76303d4f..61401e47ae 100644
--- a/src/northbridge/intel/e7525/e7525.h
+++ b/src/northbridge/intel/e7525/e7525.h
@@ -1,8 +1,3 @@
-#define VID     0X00
-#define DID     0X02
-#define PCICMD  0X04
-#define PCISTS  0X06
-#define RID	0X08
 #define IURBASE	0X14
 #define MCHCFG0	0X50
 #define MCHSCRB	0X52
diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h
index 784a8b368a..9932b9b3dd 100644
--- a/src/northbridge/intel/i440bx/i440bx.h
+++ b/src/northbridge/intel/i440bx/i440bx.h
@@ -32,19 +32,6 @@
  * Any addresses between 0x00 and 0xff not listed below are either
  * Reserved or Intel Reserved and should not be touched.
  */
-#define VID     0x00 /* Vendor Identification (0x8086). */
-#define DID     0x02 /* Device Identification (0x7190/0x7192). */
-#define PCICMD  0x04 /* PCI Command Register (0x006). */
-#define PCISTS  0x06 /* PCI Status Register (0x0210/0x0200). */
-#define RID     0x08 /* Revision Identification (0x00/0x01/0x02). */
-#define SUBC    0x0a /* Sub-Class Code (0x00). */
-#define BCC     0x0b /* Base Class Code (0x06). */
-#define MLT     0x0d /* Master Latency Timer (0x00). */
-#define HDR     0x0e /* Header Type (0x00). */
-#define APBASE  0x10 /* Aperture Base Configuration (0x00000008). */
-#define SVID    0x2c /* Subsystem Vendor Identification (0x0000). */
-#define SID     0x2e /* Subsystem Identification (0x0000). */
-#define CAPPTR  0x34 /* Capabilities Pointer (0xa0/0x00). */
 #define NBXCFG  0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
 #define DRAMC   0x57 /* DRAM Control (00S0_0000b). */
 #define DRAMT   0x58 /* DRAM Timing (0x03). */
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index b1fb77e21b..2f69a81a7f 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -503,7 +503,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	pci_write_config8(ctrl->d0, PMCR, 0x10);
 
 	/* TODO? */
-	pci_write_config8(ctrl->d0, MLT, 0x40);
+	pci_write_config8(ctrl->d0, PCI_LATENCY_TIMER, 0x40);
 	pci_write_config8(ctrl->d0, DRAMT, 0x03);
 	pci_write_config8(ctrl->d0, MBSC, 0x03);
 	pci_write_config8(ctrl->d0, SCRR, 0x38);
diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h
index d5979787cb..64a25a6e21 100644
--- a/src/northbridge/intel/i82810/i82810.h
+++ b/src/northbridge/intel/i82810/i82810.h
@@ -34,19 +34,6 @@
  * should not be touched.
  */
 
-#define VID	0x00		/* Vendor Identification */
-#define DID	0x02		/* Device Identification */
-#define PCICMD	0x04		/* PCI Command Register */
-#define PCISTS	0x06		/* PCI Status Register */
-#define RID	0x08		/* Revision Identification */
-#define SUBC	0x0a		/* Sub-Class Code */
-#define BCC	0x0b		/* Base Class Code */
-#define MLT	0x0d		/* Master Latency Timer */
-#define HDR	0x0e		/* Header Type */
-#define SVID	0x2c		/* Subsystem Vendor Identification */
-#define SID	0x2e		/* Subsystem Identification */
-#define CAPPTR	0x34		/* Capabilities Pointer */
-
 /* TODO: Descriptions. */
 #define GMCHCFG	0x50
 #define PAM	0x51