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authorFelix Held <felix-coreboot@felixheld.de>2021-04-09 20:53:19 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-04-11 21:06:45 +0000
commita643e212c28614da73b08feb47bdbe772385a437 (patch)
tree80312274134a395a5657165d9601ff6336795cfa /src/northbridge
parent70d1c723f77608ba9c4295f5eb83d17c776f826b (diff)
soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_state
Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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