src: Retype option API to use unsigned integers

The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.

Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>

7 files changed, 7 insertions, 7 deletions

diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index f7bdb2855b..7b0b1e5699 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -116,7 +116,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
 		sysinfo->ggc = 0x0002;
 	else {
 		/* 4 for 32MB, default if not set in CMOS */
-		u8 gfxsize = get_int_option("gfx_uma_size", 4);
+		u8 gfxsize = get_uint_option("gfx_uma_size", 4);
 
 		/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
 		   2MB GTT + 2MB shadow GTT (0x0b00) else. */
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b9c944169f..d730b2e628 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -149,7 +149,7 @@ static void i945_setup_bars(void)
 	pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
 
 	/* vram size from CMOS option */
-	gfxsize = get_int_option("gfx_uma_size", 2);	/* 2 for 8MB */
+	gfxsize = get_uint_option("gfx_uma_size", 2);	/* 2 for 8MB */
 	/* make sure no invalid setting is used */
 	if (gfxsize > 6)
 		gfxsize = 2;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 8aa722ccd6..0d014fbaf1 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -710,7 +710,7 @@ static void gma_func1_init(struct device *dev)
 	if (!CONFIG(NO_GFX_INIT))
 		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
-	pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff));
+	pci_write_config8(dev, 0xf4, get_uint_option("tft_brightness", 0xff));
 }
 
 static void gma_generate_ssdt(const struct device *device)
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index d8e72b9f1f..72c3028df8 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3102,7 +3102,7 @@ void chipset_init(const int s3resume)
 	mchbar_write16(0x1170, 0xb880);
 	mchbar_clrsetbits8(0x1210, ~0, 0x84);
 
-	gfxsize = get_int_option("gfx_uma_size", 0);	/* 0 for 32MB */
+	gfxsize = get_uint_option("gfx_uma_size", 0);	/* 0 for 32MB */
 
 	ggc = 0xb00 | ((gfxsize + 5) << 4);
 
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index df7dcb39e1..ae27d854a3 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -25,7 +25,7 @@ static void early_graphics_setup(void)
 	pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
 
 	/* Fetch VRAM size from CMOS option */
-	reg8 = get_int_option("gfx_uma_size", 0);	/* 0 for 8MB */
+	reg8 = get_uint_option("gfx_uma_size", 0);	/* 0 for 8MB */
 
 	/* Ensure the setting is valid */
 	if (reg8 > 6)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 51b85120c3..7acc5af845 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -87,7 +87,7 @@ static void sandybridge_setup_graphics(void)
 	printk(BIOS_DEBUG, "Initializing Graphics...\n");
 
 	/* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */
-	gfxsize = get_int_option("gfx_uma_size", 0);
+	gfxsize = get_uint_option("gfx_uma_size", 0);
 
 	reg16 = pci_read_config16(HOST_BRIDGE, GGC);
 	reg16 &= ~0x00f8;
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 1de9e2868b..410653dbe9 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -39,7 +39,7 @@ void x4x_early_init(void)
 		pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
 
 		/* Set preallocated IGD size from CMOS, or default to 64 MiB */
-		u8 gfxsize = get_int_option("gfx_uma_size", 6);
+		u8 gfxsize = get_uint_option("gfx_uma_size", 6);
 		if (gfxsize > 12)
 			gfxsize = 6;
 		/* Need at least 4M for cbmem_top alignment */