diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 11:02:48 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 20:47:27 +0000 |
| commit | 6fe3c06614dd423ad9a364c5f578e8c1764de65e (patch) | |
| tree | 4090172f6870806e388bd7ee304d0cca8c6d37d1 /src/northbridge | |
| parent | 8cc39a5fae28c02d344b2401bb489898f369929f (diff) | |
nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Broadwell uses a 32-bit or, so also use it on Haswell for consistency.
This has no effect because MRC already locks the memory controller down.
Tested on Asrock B85M Pro4, still boots and register is still locked.
Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/finalize.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1c83110a60..22f98625aa 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,6 +17,9 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); + /* Memory Controller Lockdown */ + MCHBAR32(MC_LOCK) |= 0x8f; + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ @@ -26,9 +29,6 @@ void intel_northbridge_haswell_finalize_smm(void) MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - /* Memory Controller Lockdown */ - MCHBAR8(MC_LOCK) = 0x8f; - /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); |