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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 13:39:37 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-10 17:45:47 +0000 |
| commit | 56fcfb5b4f00830d0c1bf2230e1104045d795c82 (patch) | |
| tree | 877ce586fdcf6f0acf82b9001661eba7aa1bc99b /src/northbridge | |
| parent | c0bdf89ff458f84e332aa861809a23997ce1b905 (diff) | |
soc/intel/common: Adapt XHCI elog driver for reuse
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS
or North XHCI block has a similar enough PCI MMIO structure to make this
code mostly reusable.
1) Rename everything to drop the `pch_` prefix
2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI
controller
3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI
controller
BUG=b:172279037
TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via
EC; type on keyboard, verify it wakes up, eventlog contains:
39 | 2020-12-10 09:40:21 | S0ix Enter
40 | 2020-12-10 09:40:42 | S0ix Exit
41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1
42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109
which verifies it still functions for the PCH XHCI controller
Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions