nb/intel/x4x: Prepare for x86_64 support

Do the usual type conversions

TESTED: Same image with BUILD_TIMELESS=1

Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 16 insertions, 14 deletions

diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 854e14343b..cda503ec3b 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <console/console.h>
 #include <delay.h>
+#include <stdint.h>
 #include <string.h>
 #include <types.h>
 #include "raminit.h"
@@ -169,13 +170,13 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
 				if ((count1 % 16) == 0)
 					mchbar_write32(0xf90, 1);
 				const u32 pattern = write_training_schedule[count1];
-				write32((u32 *)address + 8 * count1, pattern);
-				write32((u32 *)address + 8 * count1 + 4, pattern);
+				write32((u32 *)(uintptr_t)address + 8 * count1, pattern);
+				write32((u32 *)(uintptr_t)address + 8 * count1 + 4, pattern);
 			}
 
 			const u32 good = write_training_schedule[count];
-			write32(&data[0], read32((u32 *)address + 8 * count));
-			write32(&data[4], read32((u32 *)address + 8 * count + 4));
+			write32(&data[0], read32((u32 *)(uintptr_t)address + 8 * count));
+			write32(&data[4], read32((u32 *)(uintptr_t)address + 8 * count + 4));
 			FOR_EACH_BYTELANE(lane) {
 				u8 expected = (good >> ((lane % 4) * 8)) & 0xff;
 				if (data[lane] != expected)
@@ -352,8 +353,8 @@ static u8 test_dqs_aligned(const struct sysinfo *s, const u8 channel)
 		address = test_address(channel, rank);
 		for (i = 0; i < RT_PATTERN_SIZE; i++) {
 			const u32 good = read_training_schedule[i];
-			write32(&data[0], read32((u32 *)address + i * 8));
-			write32(&data[4], read32((u32 *)address + i * 8 + 4));
+			write32(&data[0], read32((u32 *)(uintptr_t)address + i * 8));
+			write32(&data[4], read32((u32 *)(uintptr_t)address + i * 8 + 4));
 
 			FOR_EACH_BYTELANE(lane) {
 				if (data[lane] != (good & 0xff))
@@ -441,8 +442,8 @@ int do_read_training(struct sysinfo *s)
 				address = test_address(channel, rank);
 				for (i = 0; i < RT_PATTERN_SIZE; i++) {
 					content = read_training_schedule[i];
-					write32((u32 *)address + 8 * i, content);
-					write32((u32 *)address + 8 * i + 4, content);
+					write32((u32 *)(uintptr_t)address + 8 * i, content);
+					write32((u32 *)(uintptr_t)address + 8 * i + 4, content);
 				}
 			}
 
@@ -616,8 +617,8 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank,
 
 	memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0]));
 	for (samples = 0; samples < N_SAMPLES; samples++) {
-		write32((u32 *)address, 0x12341234);
-		write32((u32 *)address + 4, 0x12341234);
+		write32((u32 *)(uintptr_t)address, 0x12341234);
+		write32((u32 *)(uintptr_t)address + 4, 0x12341234);
 		udelay(5);
 		FOR_EACH_BYTELANE(lane) {
 			u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 2245f9656f..c92fd452bd 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -72,7 +72,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* cbmem_top can be shifted downwards due to alignment.
 	   Mark the region between cbmem_top and tomk as unusable */
-	delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);
+	delta_cbmem = tomk - ((uint32_t)(uintptr_t)cbmem_top() >> 10);
 	tomk -= delta_cbmem;
 	uma_sizek += delta_cbmem;
 
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 2d70b96d5d..126a44bfcd 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1283,7 +1283,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val)
 	}
 	data32 <<= 3;
 
-	read32((void *)((data32 | addr)));
+	read32((void *)(uintptr_t)(data32 | addr));
 	udelay(10);
 	mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD);
 	mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD);
@@ -2090,7 +2090,7 @@ void do_raminit(struct sysinfo *s, int fast_boot)
 	if (s->boot_path == BOOT_PATH_NORMAL) {
 		FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
 			for (bank = 0; bank < 4; bank++)
-				read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12)));
+				read32((u32 *)(uintptr_t)(test_address(ch, r) | 0x800000 | (bank << 12)));
 		}
 	}
 	printk(BIOS_DEBUG, "Done dummy reads\n");
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 9e58ef33c0..5bb395a518 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <console/console.h>
 #include <delay.h>
+#include <stdint.h>
 #include "raminit.h"
 #include "x4x.h"
 
@@ -37,7 +38,7 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel)
 	}
 	mfence();
 	/* Read strobe */
-	read32((u32 *)addr);
+	read32((void *)(uintptr_t)addr);
 	mfence();
 	return mchbar_read8(sample_offset) >> 6 & 1;
 }